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Kernel
Kernel » Exception handling Library

Exports for Kernel. More...

Data Structures

struct  SceExcpmgrBreakpointState
 
struct  SceExcpmgrWatchpointState
 
struct  SceExcpmgrData
 
struct  SceArmWaypoint
 
struct  SceExcpmgrExceptionContext
 
struct  SceExcpmgrExceptionHandlerContext
 

Typedefs

typedef void() SceExcpmgrExceptionHandler(SceExcpmgrExceptionContext *context, SceExcpHandlingCode code)
 Exception handler used at priorities 1-7.
 

Enumerations

enum  SceExcpKind {
  SCE_EXCP_RESET = 0 , SCE_EXCP_UNDEF_INSTRUCTION = 1 , SCE_EXCP_SVC = 2 , SCE_EXCP_PABT = 3 ,
  SCE_EXCP_DABT = 4 , SCE_EXCP_UNUSED = 5 , SCE_EXCP_IRQ = 6 , SCE_EXCP_FIQ = 7
}
 
enum  SceExcpHandlingCode {
  SCE_EXCPMGR_EXCEPTION_HANDLED = 0 , SCE_EXCPMGR_EXCEPTION_NOT_HANDLED = 1 , SCE_EXCPMGR_EXCEPTION_HANDLING_CODE_2 = 2 , SCE_EXCPMGR_EXCEPTION_NOT_HANDLED_FATAL = 3 ,
  SCE_EXCPMGR_EXCEPTION_HANDLING_CODE_4 = 4
}
 
enum  SceArmWaypointEventType {
  SCE_ARM_WAYPOINT_EVENT_DIRECT_BRANCH = 0 , SCE_ARM_WAYPOINT_EVENT_INDIRECT_BRANCH = 1 , SCE_ARM_WAYPOINT_EVENT_EXCEPTION = 2 , SCE_ARM_WAYPOINT_EVENT_MEMORY_BARRIER = 3 ,
  SCE_ARM_WAYPOINT_EVENT_DEBUG_ENTRY = 4 , SCE_ARM_WAYPOINT_EVENT_DEBUG_EXIT = 5 , SCE_ARM_WAYPOINT_EVENT_UNKNOWN_6 = 6 , SCE_ARM_WAYPOINT_EVENT_UNKNOWN_7 = 7
}
 Values stored in bits 0-2 of SceArmWaypoint::event. More...
 

Functions

 VITASDK_BUILD_ASSERT_EQ (0x30, SceExcpmgrBreakpointState)
 
 VITASDK_BUILD_ASSERT_EQ (0x28, SceExcpmgrWatchpointState)
 
 VITASDK_BUILD_ASSERT_EQ (0x40, SceExcpmgrData)
 
 VITASDK_BUILD_ASSERT_EQ (0x10, SceArmWaypoint)
 
 VITASDK_BUILD_ASSERT_EQ (0x400, SceExcpmgrExceptionContext)
 
 VITASDK_BUILD_ASSERT_EQ (0x8, SceExcpmgrExceptionHandlerContext)
 
SceExcpmgrData * ksceExcpmgrGetData (void)
 Get a pointer to SceExcpmgr's internal data.
 
int ksceExcpmgrRegisterHandler (SceExcpKind kind, int priority, void *handler)
 Register an exception handler.
 

Variables

SceKernelSpinlock SceExcpmgrBreakpointState::lock
 
SceUInt32 SceExcpmgrBreakpointState::reserved
 Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.
 
SceUInt32 SceExcpmgrBreakpointState::DBGBVR0
 
SceUInt32 SceExcpmgrBreakpointState::DBGBCR0
 
SceUInt32 SceExcpmgrBreakpointState::DBGBVR1
 
SceUInt32 SceExcpmgrBreakpointState::DBGBCR1
 
SceUInt32 SceExcpmgrBreakpointState::DBGBVR2
 
SceUInt32 SceExcpmgrBreakpointState::DBGBCR2
 
SceUInt32 SceExcpmgrBreakpointState::DBGBVR3
 
SceUInt32 SceExcpmgrBreakpointState::DBGBCR3
 
SceUInt32 SceExcpmgrBreakpointState::DBGBVR4
 
SceUInt32 SceExcpmgrBreakpointState::DBGBCR4
 
SceKernelSpinlock SceExcpmgrWatchpointState::lock
 
SceUInt32 SceExcpmgrWatchpointState::reserved
 Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.
 
SceUInt32 SceExcpmgrWatchpointState::DBGWVR0
 
SceUInt32 SceExcpmgrWatchpointState::DBGWCR0
 
SceUInt32 SceExcpmgrWatchpointState::DBGWVR1
 
SceUInt32 SceExcpmgrWatchpointState::DBGWCR1
 
SceUInt32 SceExcpmgrWatchpointState::DBGWVR2
 
SceUInt32 SceExcpmgrWatchpointState::DBGWCR2
 
SceUInt32 SceExcpmgrWatchpointState::DBGWVR3
 
SceUInt32 SceExcpmgrWatchpointState::DBGWCR3
 
int SceExcpmgrData::nestedExceptionCount [4]
 Active UNDEF, PABT, or DABT exception depth on each CPU core.
 
int SceExcpmgrData::unused [4]
 Seemingly unused.
 
void * SceExcpmgrData::ExcpStackTop [4]
 Base address of each CPU core's 0x1000-byte exception stack.
 
void * SceExcpmgrData::ExcpStackBottom [4]
 Address immediately after each CPU core's exception stack, used as its initial stack pointer.
 
SceUInt32 SceArmWaypoint::raw_data
 Printed and forwarded without interpretation on FW 3.60.
 
SceUIntPtr SceArmWaypoint::pc
 Recorded source PC.
 
SceUIntPtr SceArmWaypoint::target_pc
 Recorded target PC.
 
SceUInt32 SceArmWaypoint::event
 Bit 31 marks a valid entry; bits 0-2 are one of SceArmWaypointEventType; for exception events, bits 4-7 select the subtype; bit 8 marks a link, bit 9 selects a 32-bit instruction, bit 10 marks a taken branch, and bits 11-12 select the instruction-set state.
 
uint32_t SceExcpmgrExceptionContext::r0
 
uint32_t SceExcpmgrExceptionContext::r1
 
uint32_t SceExcpmgrExceptionContext::r2
 
uint32_t SceExcpmgrExceptionContext::r3
 
uint32_t SceExcpmgrExceptionContext::r4
 
uint32_t SceExcpmgrExceptionContext::r5
 
uint32_t SceExcpmgrExceptionContext::r6
 
uint32_t SceExcpmgrExceptionContext::r7
 
uint32_t SceExcpmgrExceptionContext::r8
 
uint32_t SceExcpmgrExceptionContext::r9
 
uint32_t SceExcpmgrExceptionContext::r10
 
uint32_t SceExcpmgrExceptionContext::r11
 
uint32_t SceExcpmgrExceptionContext::r12
 
uint32_t SceExcpmgrExceptionContext::sp
 
uint32_t SceExcpmgrExceptionContext::lr
 
uint32_t SceExcpmgrExceptionContext::address_of_faulting_instruction
 LR-8 for DABT, LR-4 for PABT or ARM UNDEF, and LR-2 for Thumb UNDEF.
 
SceExcpKind SceExcpmgrExceptionContext::ExceptionKind
 The kind of exception the CPU encountered.
 
uint32_t SceExcpmgrExceptionContext::SPSR
 
uint32_t SceExcpmgrExceptionContext::CPACR
 
uint32_t SceExcpmgrExceptionContext::FPSCR
 
uint32_t SceExcpmgrExceptionContext::FPEXC
 
uint32_t SceExcpmgrExceptionContext::CONTEXTIDR
 
uint32_t SceExcpmgrExceptionContext::TPIDRURW
 
uint32_t SceExcpmgrExceptionContext::TPIDRURO
 
uint32_t SceExcpmgrExceptionContext::TPIDRPRW
 
uint32_t SceExcpmgrExceptionContext::TTBR1
 
uint32_t SceExcpmgrExceptionContext::unused68
 
uint32_t SceExcpmgrExceptionContext::DACR
 
uint32_t SceExcpmgrExceptionContext::DFSR
 
uint32_t SceExcpmgrExceptionContext::IFSR
 
uint32_t SceExcpmgrExceptionContext::DFAR
 
uint32_t SceExcpmgrExceptionContext::IFAR
 
uint32_t SceExcpmgrExceptionContext::PAR
 
uint32_t SceExcpmgrExceptionContext::TEEHBR
 
uint32_t SceExcpmgrExceptionContext::PMCR
 
uint32_t SceExcpmgrExceptionContext::PMCNTENSET
 
uint32_t SceExcpmgrExceptionContext::PMCNTENSET_2
 Second copy of PMCNTENSET.
 
uint32_t SceExcpmgrExceptionContext::PMSELR
 
uint32_t SceExcpmgrExceptionContext::PMCCNTR
 
uint32_t SceExcpmgrExceptionContext::PMUSERENR
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER0
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR0
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER1
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR1
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER2
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR2
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER3
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR3
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER4
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR4
 
uint32_t SceExcpmgrExceptionContext::PMXEVTYPER5
 
uint32_t SceExcpmgrExceptionContext::PMXEVCNTR5
 
uint32_t SceExcpmgrExceptionContext::unusedD0
 
uint32_t SceExcpmgrExceptionContext::unkD4
 
uint32_t SceExcpmgrExceptionContext::DBGSCRext
 
uint32_t SceExcpmgrExceptionContext::unusedDC [9]
 
uint64_t SceExcpmgrExceptionContext::VFP_registers [32]
 Content of floating-point registers D0-D31.
 
uint32_t SceExcpmgrExceptionContext::unk200 [128]
 
struct SceExcpmgrExceptionHandlerContext * SceExcpmgrExceptionHandlerContext::next
 Pointer to the next handler record; bit 0 preserves Thumb state.
 
SceUInt32 SceExcpmgrExceptionHandlerContext::must_be_zero
 Must be zero when registering during cold boot; otherwise unused on FW 3.60.
 

Detailed Description

Exports for Kernel.

Using this library in your project

Include the header file in your project:

#include <psp2kern/kernel/excpmgr.h>


Link the library to the executable:

SceExcpmgrForKernel_stub


Data Structure Documentation

◆ SceExcpmgrBreakpointState

struct SceExcpmgrBreakpointState
Data Fields
SceKernelSpinlock lock
SceUInt32 reserved Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.
SceUInt32 DBGBVR0
SceUInt32 DBGBCR0
SceUInt32 DBGBVR1
SceUInt32 DBGBCR1
SceUInt32 DBGBVR2
SceUInt32 DBGBCR2
SceUInt32 DBGBVR3
SceUInt32 DBGBCR3
SceUInt32 DBGBVR4
SceUInt32 DBGBCR4

◆ SceExcpmgrWatchpointState

struct SceExcpmgrWatchpointState
Data Fields
SceKernelSpinlock lock
SceUInt32 reserved Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.
SceUInt32 DBGWVR0
SceUInt32 DBGWCR0
SceUInt32 DBGWVR1
SceUInt32 DBGWCR1
SceUInt32 DBGWVR2
SceUInt32 DBGWCR2
SceUInt32 DBGWVR3
SceUInt32 DBGWCR3

◆ SceExcpmgrData

struct SceExcpmgrData
Data Fields
int nestedExceptionCount[4] Active UNDEF, PABT, or DABT exception depth on each CPU core.
int unused[4] Seemingly unused.
void * ExcpStackTop[4] Base address of each CPU core's 0x1000-byte exception stack.
void * ExcpStackBottom[4] Address immediately after each CPU core's exception stack, used as its initial stack pointer.

◆ SceArmWaypoint

struct SceArmWaypoint
Data Fields
SceUInt32 raw_data Printed and forwarded without interpretation on FW 3.60.
SceUIntPtr pc Recorded source PC.
SceUIntPtr target_pc Recorded target PC.
SceUInt32 event Bit 31 marks a valid entry; bits 0-2 are one of SceArmWaypointEventType; for exception events, bits 4-7 select the subtype; bit 8 marks a link, bit 9 selects a 32-bit instruction, bit 10 marks a taken branch, and bits 11-12 select the instruction-set state.

◆ SceExcpmgrExceptionContext

struct SceExcpmgrExceptionContext
Data Fields
uint32_t r0
uint32_t r1
uint32_t r2
uint32_t r3
uint32_t r4
uint32_t r5
uint32_t r6
uint32_t r7
uint32_t r8
uint32_t r9
uint32_t r10
uint32_t r11
uint32_t r12
uint32_t sp
uint32_t lr
uint32_t address_of_faulting_instruction LR-8 for DABT, LR-4 for PABT or ARM UNDEF, and LR-2 for Thumb UNDEF.
SceExcpKind ExceptionKind The kind of exception the CPU encountered.
uint32_t SPSR
uint32_t CPACR
uint32_t FPSCR
uint32_t FPEXC
uint32_t CONTEXTIDR
uint32_t TPIDRURW
uint32_t TPIDRURO
uint32_t TPIDRPRW
uint32_t TTBR1
uint32_t unused68
uint32_t DACR
uint32_t DFSR
uint32_t IFSR
uint32_t DFAR
uint32_t IFAR
uint32_t PAR
uint32_t TEEHBR
uint32_t PMCR
uint32_t PMCNTENSET
uint32_t PMCNTENSET_2 Second copy of PMCNTENSET.
uint32_t PMSELR
uint32_t PMCCNTR
uint32_t PMUSERENR
uint32_t PMXEVTYPER0
uint32_t PMXEVCNTR0
uint32_t PMXEVTYPER1
uint32_t PMXEVCNTR1
uint32_t PMXEVTYPER2
uint32_t PMXEVCNTR2
uint32_t PMXEVTYPER3
uint32_t PMXEVCNTR3
uint32_t PMXEVTYPER4
uint32_t PMXEVCNTR4
uint32_t PMXEVTYPER5
uint32_t PMXEVCNTR5
uint32_t unusedD0
uint32_t unkD4
uint32_t DBGSCRext
uint32_t unusedDC[9]
uint64_t VFP_registers[32] Content of floating-point registers D0-D31.
uint32_t unk200[128]

◆ SceExcpmgrExceptionHandlerContext

struct SceExcpmgrExceptionHandlerContext
Data Fields
struct SceExcpmgrExceptionHandlerContext * next Pointer to the next handler record; bit 0 preserves Thumb state.
SceUInt32 must_be_zero Must be zero when registering during cold boot; otherwise unused on FW 3.60.

Typedef Documentation

◆ SceExcpmgrExceptionHandler

typedef void() SceExcpmgrExceptionHandler(SceExcpmgrExceptionContext *context, SceExcpHandlingCode code)

Exception handler used at priorities 1-7.

Handlers are entered with context in R0 and code in R1. They transfer control to the next handler or the exception-return path and do not return to a caller.

Enumeration Type Documentation

◆ SceExcpKind

enum SceExcpKind
Enumerator
SCE_EXCP_RESET 
SCE_EXCP_UNDEF_INSTRUCTION 
SCE_EXCP_SVC 
SCE_EXCP_PABT 
SCE_EXCP_DABT 
SCE_EXCP_UNUSED 
SCE_EXCP_IRQ 
SCE_EXCP_FIQ 

◆ SceExcpHandlingCode

enum SceExcpHandlingCode
Enumerator
SCE_EXCPMGR_EXCEPTION_HANDLED 

Resume from the supplied exception context.

SCE_EXCPMGR_EXCEPTION_NOT_HANDLED 

Process an unhandled thread exception, then continue the handler chain.

SCE_EXCPMGR_EXCEPTION_HANDLING_CODE_2 

Passed on unchanged; no code that produces this value was found in the available FW 3.60 modules.

SCE_EXCPMGR_EXCEPTION_NOT_HANDLED_FATAL 

Fatal exception; panics the kernel.

SCE_EXCPMGR_EXCEPTION_HANDLING_CODE_4 

ThreadMgr queued the exception for later debug processing; the final handler follows the normal exception-return path.

◆ SceArmWaypointEventType

enum SceArmWaypointEventType

Values stored in bits 0-2 of SceArmWaypoint::event.

Enumerator
SCE_ARM_WAYPOINT_EVENT_DIRECT_BRANCH 
SCE_ARM_WAYPOINT_EVENT_INDIRECT_BRANCH 
SCE_ARM_WAYPOINT_EVENT_EXCEPTION 
SCE_ARM_WAYPOINT_EVENT_MEMORY_BARRIER 
SCE_ARM_WAYPOINT_EVENT_DEBUG_ENTRY 
SCE_ARM_WAYPOINT_EVENT_DEBUG_EXIT 
SCE_ARM_WAYPOINT_EVENT_UNKNOWN_6 
SCE_ARM_WAYPOINT_EVENT_UNKNOWN_7 

Function Documentation

◆ VITASDK_BUILD_ASSERT_EQ() [1/6]

VITASDK_BUILD_ASSERT_EQ ( 0x30  ,
SceExcpmgrBreakpointState   
)

◆ VITASDK_BUILD_ASSERT_EQ() [2/6]

VITASDK_BUILD_ASSERT_EQ ( 0x28  ,
SceExcpmgrWatchpointState   
)

◆ VITASDK_BUILD_ASSERT_EQ() [3/6]

VITASDK_BUILD_ASSERT_EQ ( 0x40  ,
SceExcpmgrData   
)

◆ VITASDK_BUILD_ASSERT_EQ() [4/6]

VITASDK_BUILD_ASSERT_EQ ( 0x10  ,
SceArmWaypoint   
)

◆ VITASDK_BUILD_ASSERT_EQ() [5/6]

VITASDK_BUILD_ASSERT_EQ ( 0x400  ,
SceExcpmgrExceptionContext   
)

◆ VITASDK_BUILD_ASSERT_EQ() [6/6]

VITASDK_BUILD_ASSERT_EQ ( 0x8  ,
SceExcpmgrExceptionHandlerContext   
)

◆ ksceExcpmgrGetData()

SceExcpmgrData * ksceExcpmgrGetData ( void  )

Get a pointer to SceExcpmgr's internal data.

Returns
A pointer to the SceExcpmgrData structure.

◆ ksceExcpmgrRegisterHandler()

int ksceExcpmgrRegisterHandler ( SceExcpKind  kind,
int  priority,
void *  handler 
)

Register an exception handler.

The address obtained by clearing bits 0-1 of handler must point to a SceExcpmgrExceptionHandlerContext immediately followed by the handler code. In handler, bit 0 selects Thumb state and bit 1 must be clear. Priorities 1-7 use the SceExcpmgrExceptionHandler prototype; priority 0 uses a raw, exception-specific vector-entry ABI.

Parameters
[in]kindThe kind of exception.
[in]priorityThe priority (must be 0 <= priority < 8), 0 highest.
[in,out]handlerA pointer to a SceExcpmgrExceptionHandlerContext followed by the handler code.
Returns
Error code or zero on success.

Variable Documentation

◆ lock [1/2]

SceKernelSpinlock SceExcpmgrBreakpointState::lock

◆ reserved [1/2]

SceUInt32 SceExcpmgrBreakpointState::reserved

Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.

◆ DBGBVR0

SceUInt32 SceExcpmgrBreakpointState::DBGBVR0

◆ DBGBCR0

SceUInt32 SceExcpmgrBreakpointState::DBGBCR0

◆ DBGBVR1

SceUInt32 SceExcpmgrBreakpointState::DBGBVR1

◆ DBGBCR1

SceUInt32 SceExcpmgrBreakpointState::DBGBCR1

◆ DBGBVR2

SceUInt32 SceExcpmgrBreakpointState::DBGBVR2

◆ DBGBCR2

SceUInt32 SceExcpmgrBreakpointState::DBGBCR2

◆ DBGBVR3

SceUInt32 SceExcpmgrBreakpointState::DBGBVR3

◆ DBGBCR3

SceUInt32 SceExcpmgrBreakpointState::DBGBCR3

◆ DBGBVR4

SceUInt32 SceExcpmgrBreakpointState::DBGBVR4

◆ DBGBCR4

SceUInt32 SceExcpmgrBreakpointState::DBGBCR4

◆ lock [2/2]

SceKernelSpinlock SceExcpmgrWatchpointState::lock

◆ reserved [2/2]

SceUInt32 SceExcpmgrWatchpointState::reserved

Ignored on FW 3.60 by Excpmgr and Intrmgr; zero in the known default state stored in BSS.

◆ DBGWVR0

SceUInt32 SceExcpmgrWatchpointState::DBGWVR0

◆ DBGWCR0

SceUInt32 SceExcpmgrWatchpointState::DBGWCR0

◆ DBGWVR1

SceUInt32 SceExcpmgrWatchpointState::DBGWVR1

◆ DBGWCR1

SceUInt32 SceExcpmgrWatchpointState::DBGWCR1

◆ DBGWVR2

SceUInt32 SceExcpmgrWatchpointState::DBGWVR2

◆ DBGWCR2

SceUInt32 SceExcpmgrWatchpointState::DBGWCR2

◆ DBGWVR3

SceUInt32 SceExcpmgrWatchpointState::DBGWVR3

◆ DBGWCR3

SceUInt32 SceExcpmgrWatchpointState::DBGWCR3

◆ nestedExceptionCount

int SceExcpmgrData::nestedExceptionCount[4]

Active UNDEF, PABT, or DABT exception depth on each CPU core.

◆ unused

int SceExcpmgrData::unused[4]

Seemingly unused.

◆ ExcpStackTop

void* SceExcpmgrData::ExcpStackTop[4]

Base address of each CPU core's 0x1000-byte exception stack.

◆ ExcpStackBottom

void* SceExcpmgrData::ExcpStackBottom[4]

Address immediately after each CPU core's exception stack, used as its initial stack pointer.

◆ raw_data

SceUInt32 SceArmWaypoint::raw_data

Printed and forwarded without interpretation on FW 3.60.

◆ pc

SceUIntPtr SceArmWaypoint::pc

Recorded source PC.

◆ target_pc

SceUIntPtr SceArmWaypoint::target_pc

Recorded target PC.

◆ event

SceUInt32 SceArmWaypoint::event

Bit 31 marks a valid entry; bits 0-2 are one of SceArmWaypointEventType; for exception events, bits 4-7 select the subtype; bit 8 marks a link, bit 9 selects a 32-bit instruction, bit 10 marks a taken branch, and bits 11-12 select the instruction-set state.

◆ r0

uint32_t SceExcpmgrExceptionContext::r0

◆ r1

uint32_t SceExcpmgrExceptionContext::r1

◆ r2

uint32_t SceExcpmgrExceptionContext::r2

◆ r3

uint32_t SceExcpmgrExceptionContext::r3

◆ r4

uint32_t SceExcpmgrExceptionContext::r4

◆ r5

uint32_t SceExcpmgrExceptionContext::r5

◆ r6

uint32_t SceExcpmgrExceptionContext::r6

◆ r7

uint32_t SceExcpmgrExceptionContext::r7

◆ r8

uint32_t SceExcpmgrExceptionContext::r8

◆ r9

uint32_t SceExcpmgrExceptionContext::r9

◆ r10

uint32_t SceExcpmgrExceptionContext::r10

◆ r11

uint32_t SceExcpmgrExceptionContext::r11

◆ r12

uint32_t SceExcpmgrExceptionContext::r12

◆ sp

uint32_t SceExcpmgrExceptionContext::sp

◆ lr

uint32_t SceExcpmgrExceptionContext::lr

◆ address_of_faulting_instruction

uint32_t SceExcpmgrExceptionContext::address_of_faulting_instruction

LR-8 for DABT, LR-4 for PABT or ARM UNDEF, and LR-2 for Thumb UNDEF.

◆ ExceptionKind

SceExcpKind SceExcpmgrExceptionContext::ExceptionKind

The kind of exception the CPU encountered.

◆ SPSR

uint32_t SceExcpmgrExceptionContext::SPSR

◆ CPACR

uint32_t SceExcpmgrExceptionContext::CPACR

◆ FPSCR

uint32_t SceExcpmgrExceptionContext::FPSCR

◆ FPEXC

uint32_t SceExcpmgrExceptionContext::FPEXC

◆ CONTEXTIDR

uint32_t SceExcpmgrExceptionContext::CONTEXTIDR

◆ TPIDRURW

uint32_t SceExcpmgrExceptionContext::TPIDRURW

◆ TPIDRURO

uint32_t SceExcpmgrExceptionContext::TPIDRURO

◆ TPIDRPRW

uint32_t SceExcpmgrExceptionContext::TPIDRPRW

◆ TTBR1

uint32_t SceExcpmgrExceptionContext::TTBR1

◆ unused68

uint32_t SceExcpmgrExceptionContext::unused68

◆ DACR

uint32_t SceExcpmgrExceptionContext::DACR

◆ DFSR

uint32_t SceExcpmgrExceptionContext::DFSR

◆ IFSR

uint32_t SceExcpmgrExceptionContext::IFSR

◆ DFAR

uint32_t SceExcpmgrExceptionContext::DFAR

◆ IFAR

uint32_t SceExcpmgrExceptionContext::IFAR

◆ PAR

uint32_t SceExcpmgrExceptionContext::PAR

◆ TEEHBR

uint32_t SceExcpmgrExceptionContext::TEEHBR

◆ PMCR

uint32_t SceExcpmgrExceptionContext::PMCR

◆ PMCNTENSET

uint32_t SceExcpmgrExceptionContext::PMCNTENSET

◆ PMCNTENSET_2

uint32_t SceExcpmgrExceptionContext::PMCNTENSET_2

Second copy of PMCNTENSET.

◆ PMSELR

uint32_t SceExcpmgrExceptionContext::PMSELR

◆ PMCCNTR

uint32_t SceExcpmgrExceptionContext::PMCCNTR

◆ PMUSERENR

uint32_t SceExcpmgrExceptionContext::PMUSERENR

◆ PMXEVTYPER0

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER0

◆ PMXEVCNTR0

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR0

◆ PMXEVTYPER1

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER1

◆ PMXEVCNTR1

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR1

◆ PMXEVTYPER2

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER2

◆ PMXEVCNTR2

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR2

◆ PMXEVTYPER3

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER3

◆ PMXEVCNTR3

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR3

◆ PMXEVTYPER4

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER4

◆ PMXEVCNTR4

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR4

◆ PMXEVTYPER5

uint32_t SceExcpmgrExceptionContext::PMXEVTYPER5

◆ PMXEVCNTR5

uint32_t SceExcpmgrExceptionContext::PMXEVCNTR5

◆ unusedD0

uint32_t SceExcpmgrExceptionContext::unusedD0

◆ unkD4

uint32_t SceExcpmgrExceptionContext::unkD4

◆ DBGSCRext

uint32_t SceExcpmgrExceptionContext::DBGSCRext

◆ unusedDC

uint32_t SceExcpmgrExceptionContext::unusedDC[9]

◆ VFP_registers

uint64_t SceExcpmgrExceptionContext::VFP_registers[32]

Content of floating-point registers D0-D31.

◆ unk200

uint32_t SceExcpmgrExceptionContext::unk200[128]

◆ next

struct SceExcpmgrExceptionHandlerContext* SceExcpmgrExceptionHandlerContext::next

Pointer to the next handler record; bit 0 preserves Thumb state.

◆ must_be_zero

SceUInt32 SceExcpmgrExceptionHandlerContext::must_be_zero

Must be zero when registering during cold boot; otherwise unused on FW 3.60.