vitasdk
Documentation of the vitasdk
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Block size fields | |
#define | SCE_KERNEL_DMAC_BLOCKSIZE_SRC_SHIFT (0) |
#define | SCE_KERNEL_DMAC_BLOCKSIZE_SRC_MASK (0x0000FFFF) |
#define | SCE_KERNEL_DMAC_BLOCKSIZE_DST_SHIFT (16) |
#define | SCE_KERNEL_DMAC_BLOCKSIZE_DST_MASK (0xFFFF0000) |
Stat fields | |
#define | SCE_KERNEL_DMAC_STAT_BUSY (0x00000001) |
#define | SCE_KERNEL_DMAC_STAT_ABORTED (0x00000002) |
#define | SCE_KERNEL_DMAC_STAT_ERROR_READ (0x00010000) |
#define | SCE_KERNEL_DMAC_STAT_ERROR_WRITE (0x00020000) |
#define | SCE_KERNEL_DMAC_STAT_ERROR_ILLEGAL_CONFIG (0x00040000) |
#define | SCE_KERNEL_DMAC_STAT_ERROR_TAG (0x00080000) |
#define | SCE_KERNEL_DMAC_STAT_ERROR_ZERO_BYTE (0x00100000) |
Coherency mask fields | |
This field, along with the SCE_KERNEL_DMAC_CMD_COHERENT_{SRC/DST} command flags, control cache coherency behavior for the src and dst.
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#define | SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_SHIFT (0) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_MASK (0x000001FF) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_DST_SHIFT (9) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_DST_MASK (0x0003FE00) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_DST_MASK (0x0003FFFF) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_UNK_SHIFT (18) |
#define | SCE_KERNEL_DMAC_COHERENCY_MSK_UNK_MASK (0x07FC0000) |
This mask is set internally by DmacMgr. It likely affects the coherency of the DMA tag reads. More... | |
IV Coherency mask fields | |
This field, along with the SCE_KERNEL_DMAC_CMD_COHERENT_IV_{READ/WRITE} command flags, control cache coherency behavior for the iv.
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#define | SCE_KERNEL_DMAC_IV_COHERENCY_MSK_READ_SHIFT (0) |
#define | SCE_KERNEL_DMAC_IV_COHERENCY_MSK_READ_MASK (0x000001FF) |
#define | SCE_KERNEL_DMAC_IV_COHERENCY_MSK_WRITE_SHIFT (16) |
#define | SCE_KERNEL_DMAC_IV_COHERENCY_MSK_WRITE_MASK (0x01FF0000) |
#define | SCE_KERNEL_DMAC_IV_COHERENCY_MSK_RW_MASK (0x01FF01FF) |
#define SCE_KERNEL_DMAC_CMD_OP_COPY (0x00000000) |
#define SCE_KERNEL_DMAC_CMD_OP_SET (0x0000000C) |
#define SCE_KERNEL_DMAC_CMD_OP_RNG (0x00000004) |
#define SCE_KERNEL_DMAC_CMD_OP_HASH_SHA1 (0x00000003) |
#define SCE_KERNEL_DMAC_CMD_OP_HASH_SHA224 (0x0000000B) |
#define SCE_KERNEL_DMAC_CMD_OP_HASH_SHA256 (0x00000013) |
#define SCE_KERNEL_DMAC_CMD_OP_HMAC_SHA1 (0x00000023) |
#define SCE_KERNEL_DMAC_CMD_OP_HMAC_SHA224 (0x0000002B) |
#define SCE_KERNEL_DMAC_CMD_OP_HMAC_SHA256 (0x00000033) |
#define SCE_KERNEL_DMAC_CMD_OP_ENCRYPT_AES_ECB (0x00000001) |
#define SCE_KERNEL_DMAC_CMD_OP_ENCRYPT_AES_CBC (0x00000009) |
#define SCE_KERNEL_DMAC_CMD_OP_ENCRYPT_AES_CTR (0x00000011) |
#define SCE_KERNEL_DMAC_CMD_OP_ENCRYPT_DES_ECB (0x00000041) |
#define SCE_KERNEL_DMAC_CMD_OP_ENCRYPT_DES_CBC (0x00000049) |
#define SCE_KERNEL_DMAC_CMD_OP_DECRYPT_AES_ECB (0x00000002) |
#define SCE_KERNEL_DMAC_CMD_OP_DECRYPT_AES_CBC (0x0000000A) |
#define SCE_KERNEL_DMAC_CMD_OP_DECRYPT_AES_CTR (0x00000012) |
#define SCE_KERNEL_DMAC_CMD_OP_DECRYPT_DES_ECB (0x00000042) |
#define SCE_KERNEL_DMAC_CMD_OP_DECRYPT_DES_CBC (0x0000004A) |
#define SCE_KERNEL_DMAC_CMD_USE_EXTERNAL_KEY (0x00000080) |
#define SCE_KERNEL_DMAC_CMD_KEYSIZE_64BIT (0x00000000) |
#define SCE_KERNEL_DMAC_CMD_KEYSIZE_128BIT (0x00000100) |
#define SCE_KERNEL_DMAC_CMD_KEYSIZE_192BIT (0x00000200) |
#define SCE_KERNEL_DMAC_CMD_KEYSIZE_256BIT (0x00000300) |
#define SCE_KERNEL_DMAC_CMD_HASH_UPDATE (0x00000400) |
#define SCE_KERNEL_DMAC_CMD_HASH_FINALIZE (0x00000800) |
#define SCE_KERNEL_DMAC_CMD_COHERENT_SRC (0x01000000) |
L2 Cache Coherent pTag->src accesses.
#define SCE_KERNEL_DMAC_CMD_COHERENT_DST (0x02000000) |
L2 Cache Coherent pTag->dst accesses.
#define SCE_KERNEL_DMAC_CMD_COHERENT_IV_READ (0x04000000) |
L2 Cache Coherent pTag->iv reads.
#define SCE_KERNEL_DMAC_CMD_COHERENT_IV_WRITE (0x08000000) |
L2 Cache Coherent pTag->iv writes.
#define SCE_KERNEL_DMAC_BLOCKSIZE_SRC_SHIFT (0) |
#define SCE_KERNEL_DMAC_BLOCKSIZE_SRC_MASK (0x0000FFFF) |
#define SCE_KERNEL_DMAC_BLOCKSIZE_DST_SHIFT (16) |
#define SCE_KERNEL_DMAC_BLOCKSIZE_DST_MASK (0xFFFF0000) |
#define SCE_KERNEL_DMAC_STAT_BUSY (0x00000001) |
#define SCE_KERNEL_DMAC_STAT_ABORTED (0x00000002) |
#define SCE_KERNEL_DMAC_STAT_ERROR_READ (0x00010000) |
#define SCE_KERNEL_DMAC_STAT_ERROR_WRITE (0x00020000) |
#define SCE_KERNEL_DMAC_STAT_ERROR_ILLEGAL_CONFIG (0x00040000) |
#define SCE_KERNEL_DMAC_STAT_ERROR_TAG (0x00080000) |
#define SCE_KERNEL_DMAC_STAT_ERROR_ZERO_BYTE (0x00100000) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_SHIFT (0) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_MASK (0x000001FF) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_DST_SHIFT (9) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_DST_MASK (0x0003FE00) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_SRC_DST_MASK (0x0003FFFF) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_UNK_SHIFT (18) |
#define SCE_KERNEL_DMAC_COHERENCY_MSK_UNK_MASK (0x07FC0000) |
This mask is set internally by DmacMgr. It likely affects the coherency of the DMA tag reads.
#define SCE_KERNEL_DMAC_IV_COHERENCY_MSK_READ_SHIFT (0) |
#define SCE_KERNEL_DMAC_IV_COHERENCY_MSK_READ_MASK (0x000001FF) |
#define SCE_KERNEL_DMAC_IV_COHERENCY_MSK_WRITE_SHIFT (16) |
#define SCE_KERNEL_DMAC_IV_COHERENCY_MSK_WRITE_MASK (0x01FF0000) |
#define SCE_KERNEL_DMAC_IV_COHERENCY_MSK_RW_MASK (0x01FF01FF) |